1. Field of the Invention
The present invention relates to a memory device including a non-volatile ferroelectric memory and a memory system using this memory device.
2. Description of the Related Art
Semiconductor memories, particularly FeRAMs using ferroelectric materials, are attracting attention as user-friendly devices providing both high speed access and non-volatile storage and offering the promise of increased capacity in the future.
An FeRAM is small in size and consumes low electric power and, at the same time, is resistant to shock. If progress is made in reducing the bit unit price along with the increase in capacity, it will also has promise as a future recording medium for sound or images.
Particularly, as promising means for improving the degree of integration, Japanese Patent Application No. 11-158632 and Japanese Unexamined Patent Publication (Kokai) No. 09-121032 propose a so-called xe2x80x9ccross point typexe2x80x9d ferroelectric memory.
FIG. 10 is a circuit diagram of an example of a cross point type ferroelectric memory.
This ferroelectric memory 10 has, as shown in FIG. 10, a memory cell array 11, word driver (WRD DRV) 12, plate (PLT DRV) driver 13, and sense amplifier (S/A) 14.
The memory cell array 11 is comprised of a plurality of (eight in FIG. 10) ferroelectric capacitors FC101 to FC108 forming individual memory cell arranged in a four-row, two-column matrix.
The memory cell array 11 is divided into two cell strings CST11 and CST12.
The cell string CST11 is configured by a pass transistor TR101 comprised of an n-channel MOS transistor and ferroelectric capacitors FC101, FC102, fC103, and FC104 arranged in the same column.
In the cell string CST11, first electrodes of the ferroelectric capacitors FC101, FC102, FC103, and FC104 serving as four memory cells are commonly connected to one node electrode ND11 connected to a bit line BL11 via the pass transistor TR101.
The other electrodes of the ferroelectric capacitors FC101, FC102, FC103, and FC104 are connected to different plate lines PL11, PL12, PL13, and PL14 to thereby enable data to be written independently in the ferroelectric capacitors FC101, FC102, FC103, and FC104 serving as the memory cells.
Note that data of the plurality of ferroelectric capacitors FC101, FC102, FC103, and FC104 sharing the node electrode ND11 is for example accessed all together continuously. Further, the accessed data is amplified by the sense amplifier 14 and rewritten.
The cell string CST12 is configured by a pass transistor TR102 comprised of an n-channel MOS transistor and ferroelectric capacitors FC105, FC106, FC107, and FC108 arranged in the same column.
In the cell string CST12, first electrodes of the ferroelectric capacitors FC105, FC106, FC107, and FC108 serving as four memory cells are commonly connected to one node electrode ND12 connected to a bit line BL12 via the pass transistor TR102.
The other electrodes of the ferroelectric capacitors FC105, FC106, FC107, and FC108 are connected to different plate lines PL11, PL12, PL13, and PL14 to thereby enable data to be independently written in the ferroelectric capacitors FC105, FC106, FC107, and FC108 serving as the memory cells.
Note that the data of the plurality of ferroelectric capacitors FC105, FC106, FC107, and FC108 sharing the node electrode ND12 is for example accessed all together continuously. Further, the accessed data is amplified by the sense amplifier 14 and rewritten.
The gate electrodes of the pass transistors TR101 and TR102 of the cell strings CST11 and CST12 are connected to a common word line WL11.
A word driver 12 supplies for example a power supply voltage Vcc+xcex1 (xcex1 is a voltage not less than the threshold voltage Vth of the pass transistor, for example 1V) to an addressed word line, i.e., WL11 in the example of FIG. 10, and holds the pass transistors in a conductive state in units of cell units.
A plate driver 13 supplies the plate lines PL11 to PL14 addressed at the time of data access with a predetermined voltage 0V or Vcc for writing or reading and rewriting data in the ferroelectric capacitor of the addressed memory cell and supplies unselected plate lines with a predetermined voltage Vcc/2.
The sense amplifier 14 is connected to the bit lines BL11 and BL12, latches, amplifies, and rewrites (refreshes) the data read to the bit lines BL11 and BL12 at the time of writing and reading.
The read operation in the ferroelectric memory 10 having such a configuration is carried out as follows.
For example, when driving the word line WL11 by the word driver 12, fixing the plate lines PL12 to PL14 to 0V by the plate driver 13, and in that state driving the plate line PL11 to Vcc, the ferroelectric capacitors FC101 and FC105 discharge to the bit lines BL11 and BL12.
The data can be read by sensing the potential difference produced by this by a differential type sense amplifier 14.
Since the cross point type ferroelectric memory has one transistor shared by a plurality of capacitors, the number of elements per bit is effectively decreased. This is effective for reducing costs.
Summarizing the problem to be solved by the invention, as explained above, while a cross point type ferroelectric memory is advantageous from the viewpoint of degree of integration, it has the following limitations.
Namely, in the above cross point type semiconductor memory, since a plurality of capacitors are connected to a common node electrode of the memory string selected by the word line, when writing data into any one capacitor, voltage is also supplied to the unselected capacitors sharing the node electrode (this will be generally referred to as a xe2x80x9cdisturbancexe2x80x9d).
The voltage supplied is not large enough to destroy the data by a single time, but if this is supplied a number of times without restraint, the data will gradually deteriorate and finally the data will be destroyed.
Accordingly, the number of disturbances has to be restricted by some measure or another.
In the above Japanese Unexamined Patent Publication (Kokai) No. 09-121032 etc., the memory is designed to be accessed in block units so as to establish an upper limit on the disturbances.
Namely, when any cell is accessed, the other cells in the same memory string which would be affected by a disturbance are also accessed and rewritten in a consecutive sequence.
Accordingly, when the number of cells connected to the common node electrode of a memory string is N, the upper limit of the number of disturbances is Nxe2x88x921 times.
In this case, however, when accessing a certain memory string, the other memory strings cannot be accessed until all of the cells connected to that string finish being read and rewritten.
Accordingly, the application of this to random access applications like that of for example a DRAM is basically impossible or results in very slow operation.
Further, general ferroelectric memories suffer from the problem of xe2x80x9cfilm fatiguexe2x80x9d. This is the deterioration of the polarization characteristic due to repeated inversion of polarization of the ferroelectric film. The number of rewrites is restricted by this.
In general, the number of rewrites of a ferroelectric film is considered to be to about 1E12 times. With use like a DRAM, therefore, the reliability cannot be guaranteed.
For the above reason, there was the problem that the cross point type ferroelectric memory was very limited in its usage.
An object of the present invention is to provide a memory device able to make use of the non-volatility and high integration of a cross point type ferroelectric memory and yet able to improve the random accessibility of the same, reduce the number of rewrites, and facilitate control of the upper limit of disturbances and a memory system using the same.
To attain the above object, according to a first aspect of the present invention, there is provided a memory system having a first memory and a second memory, wherein the first memory has at least one bit line, at least one word line, a plurality of plate lines, and at least one cell string having a node electrode, a pass transistor connected between the bit line and the node electrode and held in a conductive state or a nonconductive state in accordance with a voltage supplied to the word line, and a plurality of ferroelectric capacitors having first electrodes commonly connected to the node electrode and other electrodes connected to different plate lines; the second memory includes a random accessible write back type cache memory; and the first memory is accessed via the second memory.
Preferably, the second memory includes a dynamic or static RAM.
Alternatively, the memory system is provided with the function of transferring in a block all of the data in units of memory strings sharing the node electrode in the first memory to the second memory.
Alternatively, the memory system is provided with the function of transferring in a block all of the data in units of cell units including a plurality of memory strings sharing the plate lines in the first memory to the second memory.
Alternatively, the memory system is provided with the function of transferring in a block all of the data in units of memory strings sharing the node electrode in the first memory from the second memory to the first memory.
Alternatively, the memory system is provided with the function of transferring in a block all of the data in units of cell units including a plurality of memory strings sharing the plate lines in the first memory from the second memory to the first memory together.
Alternatively, the first memory has the function of omitting re-storage of data into an accessed ferroelectric capacitor when reading the data.
According to a second aspect of the present invention, there is provided a memory device comprising at least one bit line; at least one word line; a plurality of plate lines; and at least one cell string having a node electrode, a pass transistor connected between the bit line and the node electrode and held in a conductive state or a nonconductive state in accordance with a voltage supplied to the word line, and a plurality of ferroelectric capacitors having first electrodes commonly connected to the node electrode and other electrodes connected to different plate lines; and having the function of omitting a re-storage of data into an accessed ferroelectric capacitor when reading data.
According to a third aspect of the present invention, there is provided a memory device having a first memory region and a second memory region, wherein the first memory region has at least one bit line, at least one word line, a plurality of plate lines, and at least one cell string having a node electrode, a pass transistor connected between the bit line and the node electrode and held in a conductive state or a nonconductive state in accordance with a voltage supplied to the word line, and a plurality of ferroelectric capacitors having first electrodes commonly connected to the node electrode and other electrodes connected to different plate lines; and the second memory region includes a random accessible memory connected to the same bit line as that for the first memory region and has the function of transferring at least part of the data from the first memory region to the second memory region.
Preferably, the memory device is provided with the function of transferring in a block all of the data in units of memory strings sharing the node electrode in the first memory region to the second memory.
Alternatively, the memory device is provided with the function of transferring in a block all of the data in units of cell units including a plurality of memory strings sharing the plate lines in the first memory region to the second memory.
Alternatively, the memory device is provided with the function of transferring in a block all of the data in units of memory strings sharing the node electrode in the first memory region from the second memory to the first memory.
Alternatively, the memory device is provided with the function of transferring in a block all of the data in units of cell units including a plurality of memory strings sharing the plate lines in the first memory region from the second memory to the first memory together.
Alternatively, the memory device further comprises a sense amplifier connected to each bit line and a latch circuit connected to each bit line and has the function of enabling access to data stored in the latch circuit from the outside while transferring data between the first memory region and the second memory region.
Alternatively, the randomly accessibly memory of the second memory region includes capacitors as storage elements, and insulation films or ferroelectric films of cell capacitors forming the second memory region are formed simultaneously with at least part of the ferroelectric films of the cell capacitors forming the first memory region.
According to the present invention, the data of the cross point type ferroelectric memory is accessed via a write back type cache memory.
Due to this, it becomes possible to freely access the data in the cache memory at random. At the same time, the cross point type memory is accessed only at the time of miss hit, and the number of data rewrites can be greatly reduced.
Further, data is transferred between the cross point type ferroelectric memory and the cache memory in units of at least the memory strings or units sharing the plate lines. Due to this, the cross point type memory side is always accessed in blocks of units.
Accordingly, the upper limit of the number of disturbances can be easily controlled.
Further, by suitably building in the above cache memory in the cross point type ferroelectric memory, the system performance can be further improved.
For example, the cache memory is made a DRAM and connected to the bit line the same as that for the memory unit of the cross point type ferroelectric memory.
The data of the DRAM is usually accessed from the outside. Due to this, the selected data of the selected unit group can be transferred directly to the DRAM in a block while keeping the area overhead to a minimum and therefore the overhead accompanying data transfer at the time of a miss hit can be greatly reduced.
Further, by forming the capacitor insulation film of the DRAM simultaneously with the ferroelectric film of at least part of the memory unit in the main memory, a miniature DRAM can be mounted without increasing the number of production steps, and the increase of the chip area accompanying the mounting of the cache can be suppressed.
Further, when the cache memory is made not by a DRAM, but by an FeRAM wherein each capacitor is separated by a transistor, the capacitor area can be reduced by the amount of use of a polarization inversion signal and therefore the overhead of the chip area is further reduced.
Further, if data is transferred between the DRAM (FeRAM) region and the cross point type ferroelectric memory region in units of unit arrays, since the cross point type ferroelectric memory region is always accessed in units of unit arrays, the upper limit of the disturbances can be easily set.
Further, by separately providing a latch in addition to the sense amplifier corresponding to each bit line, it becomes possible to transfer data between the cross point type memory region and the DRAM region while accessing data stored in the latches from the outside and thereby improve the usage efficiency of the memory.
Accordingly, if employing the present invention, it is possible to make the most of the non-volatility and high integration of the cross point type ferroelectric memory while improving the random accessibility and reducing the number of rewrites. By this, it becomes possible to greatly increase the range of applications of this memory.